---------------------------------------------------------------- | | | | | Motorola | | | | 666 88888 000 5555555 | | 6 8 8 0 0 5 | | 6 8 8 0 0 0 5 | | 666666 88888 0 0 0 555555 | | 6 6 8 8 0 0 0 5 | | 6 6 8 8 0 0 5 | | 66666 88888 000 555555 | | | | 6805 MICROPROCESSOR Instruction Set Summary | | | | | | | | | | | | _________ _________ | | _| \__/ |_ | | Vss |_|1 40|_| PA7 <--> | | _____ _| |_ | | --> RESET |_|2 39|_| PA6 <--> | | ___ _| |_ | | --> INT |_|3 38|_| PA5 <--> | | _| |_ | | Vcc |_|4 37|_| PA4 <--> | | _| |_ | | --> EXTAL |_|5 36|_| PA3 <--> | | _| |_ | | --> XTAL |_|6 35|_| PA2 <--> | | _| |_ | | NUM |_|7 34|_| PA1 <--> | | _| |_ | | --> TIMER |_|8 33|_| PA0 <--> | | _| |_ | | <--> PC0 |_|9 32|_| PB7 <--> | | _| |_ | | <--> PC1 |_|10 MC6805U2 31|_| PB6 <--> | | _| |_ | | <--> PC2 |_|11 30|_| PB5 <--> | | _| |_ | | <--> PC3 |_|12 29|_| PB4 <--> | | _| |_ | | <--> PC4 |_|13 28|_| PB3 <--> | | _| |_ | | <--> PC5 |_|14 27|_| PB2 <--> | | _| |_ | | <--> PC6 |_|15 26|_| PB1 <--> | | _| |_ | | <--> PC7 |_|16 25|_| PB0 <--> | | _| |_ | | <--> PD7 |_|17 24|_| PD0 <--> | | ____ _| |_ | | <--> PD6/INT2 |_|18 23|_| PD1 <--> | | _| |_ | | <--> PD5 |_|19 22|_| PD2 <--> | | _| |_ | | <--> PD4 |_|20 21|_| PD3 <--> | | |______________________| | | | | | | | | | | | | | |Written by Jonathan Bowen | | Programming Research Group | | Oxford University Computing Laboratory | | 8-11 Keble Road | | Oxford OX1 3QD | | England | | | | Tel +44-865-273840 | | | |Created August 1981 | |Updated April 1985 | |Issue 1.1 Copyright (C) J.P.Bowen 1985| ---------------------------------------------------------------- ---------------------------------------------------------------- |Mnemon.|Op|HINZC|IXED#RBT|Description |Notes | |-------+--+-----+--------+-----------------------+------------| |ADC s|F9|*-***| XXXX |Add with Carry |A=A+s+C | |ADD s|FB|*-***| XXXX |Add |A=A+s | |AND s|F4|--**-| XXXX |Logical AND |A=A&s | |ASL d|78|--***| X X |Arithmetic Shift Left |d=d*2 | |ASLA |48|--***|X |Arithmetic Shift Left |A=A*2 | |ASLX |58|--***|X |Arithmetic Shift Left |X=X*2 | |ASR d|77|--***| X X |Arithmetic Shift Right |d=d/2 | |ASRA |47|--***|X |Arithmetic Shift Right |A=A/2 | |ASRX |57|--***|X |Arithmetic Shift Right |X=X/2 | |BCC a|24|-----|X |Branch if Carry Clear |If C=0 | |BCLR b|11|-----| X |Bit Clear |b=0 | |BCS a|25|-----| X |Branch if Carry Set |If C=1 | |BEQ a|27|-----| X |Branch if Equal |If Z=1 | |BHCC a|28|-----| X |Branch if Half C. Clear|If H=0 | |BHCS a|29|-----| X |Branch if Half C. Set |If H=1 | |BHI a|22|-----| X |Branch if Higher |If CvZ=0 | |BHS a|24|-----| X |Branch if Higher/Same |If C=0 | |BIH a|2F|-----| X |Branch if Int. High |If I=1 | |BIL a|2E|-----| X |Branch if Int. Low |If I=0 | |BIT s|F5|--**-| XXXX |Bit Test |A&s | |BLO a|25|-----| X |Branch if Lower |If C=1 | |BLS a|23|-----| X |Branch if Lower or Same|If CvZ=1 | |BMC a|2C|-----| X |Branch if Mask Clear |If I=0 | |BMI a|2B|-----| X |Branch if Minus |If N=1 | |BMS a|2D|-----| X |Branch if Mask Set |If I=1 | |BNE a|26|-----| X |Branch if Not Equal |If Z=0 | |BPL a|2A|-----| X |Branch if Plus |If N=0 | |BRA a|20|-----| X |Branch Always |PC=a | |BRN a|21|-----| X |Branch Never |No operation| |BRCLR c|01|-----| X|Test for Bit Clear |If b=0 | |BRSET c|00|-----| X|Test for Bit Set |If b=1 | |BSET b|10|-----| X |Bit Set |b=1 | |BSR a|AD|-----|X |Branch to Subroutine |-[SP]=PC,BRA| |CLC |98|----0|X |Clear Carry |C=0 | |CLI |9A|-0---|X |Clear Interrupt Mask |I=0 | |CLR d|7F|--010| X X |Clear |d=0 | |CLRA |4F|--010|X |Clear Accumulator |A=0 | |CLRX |5F|--010|X |Clear Index register |X=0 | |CMP s|F1|--***| XXXX |Compare |A-s | |COM d|73|--**1| X X |Complement |d=~d | |COMA |43|--**1|X |Complement Accumulator |A=~A | |COMX |43|--**1|X |Complement Index reg. |X=~X | |CPX s|F3|--***|X |Compare Index register |X-s | |DEC d|7A|--**-| X X |Decrement |d=d-1 | |DECA |4A|--**-|X |Decrement Accumulator |A=A-1 | |DECX |5A|--**-|X |Decrement Index reg. |X=X-1 | |EOR s|F8|--**-| XXXX |Logical Exclusive OR |A=Axs | |INC d|7C|--**-| X X |Increment |d=d+1 | |INCA |4C|--**-|X |Increment Accumulator |A=A+1 | |INCX |5C|--**-|X |Increment Index reg. |X=X+1 | |JMP d|FC|-----| XXX |Jump |PC=d | |JSR d|FD|-----| XXX |Jump to Subroutine |-[SP]=PC,JMP| |LDA s|F6|--**-| XXXX |Load Accumulator |A=s | |LDX s|FE|--**-| XXXX |Load Index register |X=s | |LSL d|78|--0**| X X |Logical Shift Left |d={C,d,0}<- | |LSLA |48|--0**|X |Logical Shift Left |A={C,A,0}<- | |LSLX |58|--0**|X |Logical Shift Left |X={C,X,0}<- | |LSR d|74|--0**| X X |Logical Shift Right |d=->{C,d,0} | |LSRA |44|--0**|X |Logical Shift Right |A=->{C,A,0} | |LSRX |54|--0**|X |Logical Shift Right |X=->{C,X,0} | |NEG d|70|?-***| X X |Negate |d=-d | |NEGA |40|?-***|X |Negate Accumulator |A=-A | |NEGX |50|?-***|X |Negate Index register |X=-X | |NOP |9D|-----|X |No Operation | | |ORA s|FA|--**-| XXXX |Logical inclusive OR |A=Avs | |ROL d|79|--***| X X |Rotate Left |d={C,d}<- | |ROLA |49|--***|X |Rotate Left Accumulator|A={C,A}<- | |ROLX |59|--***|X |Rotate Left Index reg. |X={C,X}<- | |ROR d|76|--***| X X |Rotate Right |d=->{C,d} | |RORA |46|--***|X |Rotate Right Acc. |A=->{C,A} | |RORX |56|--***|X |Rotate Right Index reg.|X=->{C,X} | |RSP |9C|-----|X |Reset Stack Pointer |SP=007EH | |RTI |80|?????|X |Return from Interrupt |{regs}=[SP]+| |RTS |81|-----|X |Return from Subroutine |PC=[SP]+ | |SBC s|F2|--***| XXXX |Subtract with Carry |A=A-s-C | |SEC |99|----0|X |Set Carry |C=1 | ---------------------------------------------------------------- ---------------------------------------------------------------- |Mnemon.|Op|HINZC|I#DEXRBT|Description |Notes | |-------+--+-----+--------+-----------------------+------------| |SEI |9B|-0---|X |Set Interrupt Mask |I=1 | |STA d|F7|--**-| XXX |Store Accumulator |d=A | |STX d|FF|--**-| XXX |Store Index register |d=X | |SUB s|F0|--***| XXXX |Subtract |A=A-s | |SWI |83|-----|X |Software Interrupt | | |TAX |97|-----|X |Transfer Acc. to Index |X=A | |TST s|7D|--**-| X X |Test zero or minus |s | |TSTA |4D|--**-|X |Test Accumulator |A | |TSTX |5D|--**-|X |Test Index register |X | |TXA |9F|-----|X |Transfer Index to Acc. |A=X | |----------+-----+--------+------------------------------------| | CC |-*01?| |Unaffect/affected/reset/set/unknown | | H |H | |Half carry (Bit 4) | | I | I | |IRQ interrupt mask (Bit 3) | | N | N | |Negative (Bit 2) | | Z | Z | |Zero (Bit 1) | | C | C| |Carry/borrow (Bit 0) | |----------------+--------+------------------------------------| | |I |Inherent | | X | X |Index (no offset, Op=X) | | n,X | X |Index (8-bit offset, Op=X-10H) | | nn,X | X |Index (16-bit offset, Op=X-20H) | | nn,E | E |Extended (Op=X-30H) | | nn | E | ditto when EXTEND is default | | n,D | D |Direct (Op=X-40H) | | n | D | ditto when DIRECT is default | | #n | # |Immediate (Op=X-50H) | | a | R |Relative (PC=PC+2+offset) | | b | B |Bit set/clear | | c | T|Bit test and branch | |-------------------------+------------------------------------| |DIRECT |Direct addressing mode | |EXTEND |Extended addressing mode | |FCB n |Form Constant Byte | |FCC 'string' |Form Constant Characters | |FDB nn |Form Double Byte | |RMB nn |Reserve Memory Bytes | |-------------------------+------------------------------------| | A |Accumulator (8-bit) | | CC |Condition Code register (8-bit) | | PC |Program Counter (11-bit) | | SP |Stack Pointer (11-bit, 61H to 7FH) | | X |Index register (8-bit) | |-------------------------+------------------------------------| | a |Relative address (-125 to +129) | | b |Bit (0 to 7), byte (0 to 255) | | c |Bit, byte, relative address | | d |Destination | | n |8-bit expression (0 to 255) | | nn |16-bit expression (0 to 65535) | | r |Register A or X | | s |Source | | string |String of ASCII characters | |-------------------------+------------------------------------| | + |Arithmetic addition | | - |Arithmetic subtraction | | * |Arithmetic multiplication | | / |Arithmetic division | | & |Logical AND | | ~ |Logical NOT | | v |Logical inclusive OR | | x |Logical exclusive OR | | <- |Rotate left | | -> |Rotate right | | [ ] |Indirect addressing | | [ ]+ |Indirect addressing, auto-increment | | -[ ] |Auto-decrement, indirect addressing | | { } |Combination of operands | | {regs} |All registers {PC,X,A,CC} | | $ |Program Counter content | |-------------------------+------------------------------------| | 0061H to 007FH |Reserved for stack (see RSP) | | FFF8H to FFF9H |Hardware interrupt vector | | FFFAH to FFFBH |SWI instruction interrupt vector | | FFFCH to FFFDH |Non-maskable interrupt vector | | FFFEH to FFFFH |Reset vector | ---------------------------------------------------------------